The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a network router 10 is shown in accordance with the prior art. Router 10 includes a switch 12. Switch 12 includes a plurality of communication port modules 14-0 . . . 14-6, which are collectively referred to as port modules 14. Although seven port modules 14 are shown, it should be appreciated that more or fewer port modules 14 may be used. Ports 14-0 through 14-4 communicate with associated physical layer devices 16-0 through 16-4. Physical layer devices 16-0 . . . 16-3 are depicted as AC-coupled links such as 10/100-BASET, however it should be appreciated that other types of physical layers may also be employed. Physical layer devices 16-0 . . . 16-3 include respective connectors 18-0 . . . 18-3 that couple with respective network channels, such as copper cables and or/antennas. Physical layer device 16-4 is depicted as a 100/1000 Mbit laser, however it should be appreciated that another type of physical layer may also be employed. Physical layer device 16-4 includes a respective connector 18-4 that couples with a respective network channel, such as fiber-optic cables.
Switch 12 includes a switch core module 20. Switch core module 20 routes data packets between port modules 14 based on link layer information that is included in the packets. Switch core module 20 includes an ingress processing module 22, a queuing module 24, and an egress processing module 26. Ingress processing module 22 performs switching functionality on incoming packets. Queuing module 24 stores packets. Egress module 26 performs packet modification and transmits each packet to an appropriate destination port 14. A clock (CLK) 27 establishes a frequency that egress module 26 transmits the data in each packet.
A central processing unit (CPU) 30 communicates with switch 12. CPU 30 can include firmware which implements first and second media access control (MAC) modules 32-1 and 32-2, collectively 32. CPU 30 may also communicate with a network layer via an input/output data bus 40. CPU 30 includes a media data clock (MDC) and a media data input/output pin (MDIO) that provide synchronous communication with switch 12. CPU 30 also includes a communication interface for each MAC 32. The communication interfaces carry the packets between each MAC 32 and its associated one of port modules 14. Examples of communication interfaces include media independent interface (MII) reduced MII (RMII), gigabit MII (GMII), reduced gigabit MII (RGMII), 10 gigabit MII (XGMII), and serial gigabit MII (SGMII), Ethernet, fiber optic, wide area network (WAN), and the like.
A light emitting diode (LED) array 46 indicates a status and/or speed of associated port modules 14. The LED array 46 can be controlled by switch 12. An oscillator 48 drives a clock of switch 12.
During operation of router 10, data packets enter port modules 14 and pass to switch core module 20. Switch core module 20 passes the data packet to CPU 30. CPU 30 inspects network address information contained in the packets to determine which one of port modules 14 each packet should be routed to. CPU 30 then inserts routing data in each packet. The routing data corresponds with the one of port modules 14 that the packet will be routed to. CPU 30 then passes the packets back to switch core module 20. Switch core module 20 stores and forwards the packet in accordance with the inserted routing data.